At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.

Atom Computing is seeking a Principal ASIC Designer to lead the development of critical technologies that power our neutral-atom quantum computers. In this role, you will own the end-to-end design strategy—from requirements definition through silicon bring-up—while driving critical trade-off decisions across performance, power, area, and system integration.

As our first ASIC hire, you will provide strategic guidance to executive stakeholders, shaping our long-term silicon roadmap and defining our internal design methodologies. This position requires deep expertise in mixed-signal ASIC development and a "systems-first" mindset. Reporting to the Hardware Engineering Manager, you’ll collaborate with a world-class group of physicists and engineers to translate quantum gate requirements into production-ready silicon.

This position may be based in Boulder, CO, or Austin, TX.

Job Responsibilities:

• Establish Internal Processes: Define ASIC design methodologies across CAD flow selection, architecture, RTL, verification, and tape-out.

• Vendor & Strategy Ownership: Evaluate and select external partners (Design Houses vs. Pure-play Foundries) and manage the tape-out path (MPW vs. Dedicated mask sets).

• Modeling & Simulation: Develop high-level behavioral models (Matlab/SystemVerilog) to simulate the entire control loop and RF signal chain before committing to silicon.

• Hands-on Design: Lead microarchitecture and RTL development for proprietary, low-latency RF pulse sequence generation.

• Verification Leadership: Own the Universal Verification Methodology (UVM) strategy and formal verification to ensure first-pass functional success.

• Cross-Functional Collaboration: Partner with quantum physicists and optical engineers to understand use cases and deliver hardware that meets stringent fidelity requirements.

• Roadmap Management: Manage subsystem delivery schedules for both commercial and research projects.

Experience & Education

• MS or PhD in Electrical Engineering or a related field.
• 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments.

Qualifications

• ASIC Lifecycle: Proven track record of leading at least 2 complete, full-flow tape-outs.
• Mixed-Signal Expertise: Deep experience with high-speed ADCs/DACs (GSPS+) and direct RF sampling architectures.
• Node Experience: Familiarity with nodes optimized for Analog/RF (e.g., TSMC 28nm/16nm or GlobalFoundries FDX).
• Verification Mastery: Deep understanding of constrained-random verification (UVM) and hardware-in-the-loop testing.
• Tools: Expert-level proficiency with Cadence Virtuoso, Synopsys, or Siemens EDA design suites.
• Startup Mindset: Self-motivated, collaborative, and comfortable with the ambiguity of a fast-growing, early-stage company.
• Bonus: Experience with cryogenic CMOS, software-defined radio (SDR), or quantum control systems.